The creation of complex integrated circuits and semiconductor devices can be a very expensive undertaking given the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read only memories and/or EEPROMS into which software, in the form of firmware, is encoded. Further, integrated circuits are often used in applications involving the encryption of information, therefore, in order to keep such information confidential, it can be desirable to keep such devices from being reverse engineered. Thus, there can be a variety of reasons for protecting integrated circuits and other semiconductor devices from being reversed engineered.
In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique is to make the connections between transistors difficult to determine forcing the reverse engineer to carefully analyze each transistor (in particular, each CMOS transistor pair for CMOS devices), and thwarting attempts to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to carefully analyze each transistor in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
A conductive layer, such as silicide, is often used during the manufacturing of semiconductor devices. In modern CMOS devices, especially with feature sizes below 0.5 μm, a silicide layer is utilized to improve the conductivity of gate, source and drain contacts. In accordance with general design rules, any implant region using a source/drain implant is silicided.
One common reverse engineering technique involves de-layering the completed IC by means of chemical mechanical polishing (CMP). The CMP process may, under some conditions, reveal the regions between where the silicide was formed and where it was not, i.e., the regions defined by the silicide block mask step. These regions may be revealed because, under some kinds of chemical etches, there is an observable difference in topology due to different etching rates for silicided areas versus pure silicon areas. The reverse engineer, by noting the silicided areas versus non-silicided areas, may make reasonable assumptions as to the function of the device. This information can then be stored into a database for automatic classification of other similar devices.
Some methods of protecting against reverse engineering may be susceptible to discovery under some reverse engineering techniques, such as CMP. For example, FIGS. 1A and 1B depict artifacts after CMP processing of transistors made in accordance with U.S. Pat. Nos. 5,783,846; 5,930,663; and 6,064,110. U.S. Pat. Nos. 5,783,846; 5,930,663; and 6,064,110 disclose hiding the connection of doped circuit elements 26, 22 (i.e. source/drain areas) of like conductivity with electrically conductive doped implants 23-25 in the substrate, as shown in FIG. 1A. The electrically conductive doped implants 23-25 in the substrate may be provided during the same processing step as the source/drain regions and, as such, have the same doping levels and are similarly silicided. In addition, as shown in FIG. 1B, to further confuse the reverse engineer, an electrically conductive doped implant is selectively doped with a different conductivity type, creating a channel block structure 27, which prevents the electrical connection from one doped circuit element to another. In order to prevent the electrical connection from one doped circuit element 26 to another 22 via the silicide, the silicide block mask is modified. Instead of allowing a silicide layer to occur over any implant region using a source/drain implant, the silicide block mask is modified to prevent a silicide layer over the channel block structure 27.
FIGS. 1A and 1B depict artifact edges 28 of the silicide by the broken lines shown thereon. In FIG. 1A, the silicide is allowed to cover the all of the doped regions 22-26 because all of the doped regions 22-26 are doped with like conductivity type dopants. In FIG. 1B, a silicide block mask is used to prevent silicide from covering doped region 27. A reverse engineer, after a suitable stain/etch on the bare silicon surface, may be able to view this area and detect the artifact edges 28 of the silicide, which are produced at the interfaces of the silicided versus non-silicided regions. For the structure depicted by FIG. 1B, the reverse engineer could possibly conclude that when the artifact edge 28 is as shown, with an interruption 30 between the two depicted silicided portions, that such an interruption 30 would denote that the underlying conductive implants include a non-conductive channel block structure 27. This information could then be entered into a data base and automatic pattern recognition techniques could be used to recognize the pattern with the interruption 30 as being indicative of a non-conductive channel block structure 27. Thus, the effectiveness of this circuit camouflage technique is diminished.
Therefore a need exists to provide a semiconductor device and a method of manufacturing semiconductor devices that uses artifact edges to confuse the reverse engineer. Providing artifact edges that are not indicative of the actual device formed will further confuse the reverse engineer and result in incorrect conclusions as to the actual composition, and thus function, of the device.